It is known that a complementary MOSFET (CMOS) consisting of NMOS and PMOS is a major device of an IC. With the size of devices that is getting smaller, a P.sup.+ -type polysilicon gate is required for imparting the PMOS with a feature of surface channel, so as to avoid therefor short channel effect. BF.sub.2.sup.+ ions are usually implanted for simultaneously forming the P.sup.+ polysilicon gate and a P.sup.+ -N shallow junction. However, fluorine ions will enhance the penetration of boron ions through gate oxide which introduces boron ions to a Si substrate under the gate oxide. As a result, the reliability of the device is degraded, such as the increase of threshold voltage in a positive direction, and the enlargement of interface state density and charge trapping rate of the gate oxide layer.
There are papers suggesting that by means of growing or annealing the gate oxide with N.sub.2 O, or annealing the gate oxide with NH.sub.3, the boron penetration can be suppressed by the nitride layer of gate oxide interface, but N.sub.2 O grown or annealed gate oxide layer is not effective concerning suppressing boron penetration. On the other hand, the NH.sub.3 -annealed gate oxide degrades reliability of the device due to the involvement of hydrogen. Additionally, there is also proposed to use amorphous silicon gate to suppress boron penetration. Since amorphous silicon grows very slow and tends to block up the gas pipeline in LPCVD, so it is not suitable for industrial mass production.